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    Probes for testing integrated electronic circuits and corresponding production method
    1.
    发明授权
    Probes for testing integrated electronic circuits and corresponding production method 有权
    集成电子电路检测探针及相应的生产方法

    公开(公告)号：US09229031B2

    公开(公告)日：2016-01-05

    申请号：US13106615

    申请日：2011-05-12

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/20 ,  G01R1/067 ,  G01R3/00 ,  G01R31/319 ,  G01R1/073

    CPC classification number: G01R3/00 ,  G01R1/06761 ,  G01R1/07307 ,  G01R1/07342 ,  G01R31/31905 ,  Y10T29/49002

    Abstract: An embodiment of a method is proposed for producing cantilever probes for use in a test apparatus of integrated electronic circuits; the probes are configured to contact during the test corresponding terminals of the electronic circuits to be tested. An embodiment comprises forming probe bodies of electrically conductive materials. In an embodiment, the method further includes forming on a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

    Abstract translation: 提出了一种用于制造用于集成电子电路的测试装置的悬臂探针的方法的实施例; 探针被配置为在测试的电子电路的相应端子的测试期间接触。 一个实施例包括形成导电材料的探针体。 在一个实施例中，该方法还包括在每个探针体的下部形成在使用中的，被引导到要接触的相应端子的第一硬度值等于或大于300HV的导电接触区域; 每个接触区域和相应的探针体形成相应的探针。

    Method for an improved checking of repeatability and reproducibility of a measuring chain for semiconductor device testing
    2.
    发明授权
    Method for an improved checking of repeatability and reproducibility of a measuring chain for semiconductor device testing 有权
    用于半导体器件测试的测量链的重复性和再现性的改进的检查方法

    公开(公告)号：US08928346B2

    公开(公告)日：2015-01-06

    申请号：US13092772

    申请日：2011-04-22

    Applicant: Sergio Tenucci ,  Alberto Pagani ,  Marco Spinetta ,  Bernard Ranchoux

    Inventor： Sergio Tenucci ,  Alberto Pagani ,  Marco Spinetta ,  Bernard Ranchoux

    IPC: G01R31/26 ,  G05B19/418 ,  G01R31/28

    CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

    Abstract: A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.

    Abstract translation: 一种方法提供了对测量链的重复性和再现性的改进的检查，特别是通过半导体器件测试的质量控制。 该方法包括对通过测量系统进行测量或控制的多个和不同设备提供的测试步骤，所述测量系统包括测试装置（ATE）和要进行测量或控制的每个设备之间的至少一个测量单元链。 有利地，该方法包括检查构成测量链的一部分的每种类型的单元的重复性和再现性，并且在检查之后，使各种测量链之间的相关性作为整体来检查重复性和再现性，使用受到 测量或控制。

    Electromagnetic shield for testing integrated circuits
    3.
    发明授权
    Electromagnetic shield for testing integrated circuits 有权
    用于测试集成电路的电磁屏蔽

    公开(公告)号：US08907693B2

    公开(公告)日：2014-12-09

    申请号：US12851680

    申请日：2010-08-06

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/28 ,  G01R1/18 ,  G01R1/067 ,  G01R1/073

    CPC classification number: G01R1/18 ,  G01R1/06772 ,  G01R1/07307 ,  G01R31/2884 ,  G01R31/2886

    Abstract: An embodiment of a probe card is proposed. The probe card comprises a plurality of probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. Said plurality of probes includes at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. Said probe card comprises at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.

    Abstract translation: 提出了一种探针卡的实施例。 探针卡包括多个探针。 每个探针适于在晶片的测试阶段期间接触集成在半导体材料晶片的至少一个管芯中的电路的相应端子。 所述多个探头包括适于在测试阶段期间向/从相应终端提供和/或接收射频测试信号的至少一个探头。 所述探针卡包括对应于所述至少一个探头的至少一个电磁屏蔽结构，所述至少一个探针适于提供和/或接收射频测试信号，用于对由至少一个探头照射的电磁场的至少部分屏蔽， /或接收射频测试信号。

    CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER
    5.
    发明申请
    CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER 有权
    用于在半导体波形集成的大量电子器件进行电气或电磁测试期间并联供电的电路架构

    公开(公告)号：US20110186838A1

    公开(公告)日：2011-08-04

    申请号：US13022419

    申请日：2011-02-07

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: H01L23/48 ,  H01L21/66

    CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

    Abstract translation: 电路架构提供了在同一半导体晶片上并且由划线界定的电子设备的电或电磁测试期间并联供电。 电路架构包括将电子设备互连并且具有设备外部的部分和设备内部的部分的导电栅格。 外部部分沿划线延伸; 并且内部部分在装置的至少一部分内延伸。 电路结构包括在导电栅格的外部部分和内部部分之间并且设置在至少一部分器件上的互连焊盘，互连焊盘与内部和外部部分形成不同的电源线 电子设备组。

    METHOD FOR PERFORMING AN ELECTRICAL TESTING OF ELECTRONIC DEVICES
    6.
    发明申请
    METHOD FOR PERFORMING AN ELECTRICAL TESTING OF ELECTRONIC DEVICES 有权
    用于执行电子设备电气测试的方法

    公开(公告)号：US20100134133A1

    公开(公告)日：2010-06-03

    申请号：US12625188

    申请日：2009-11-24

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/02

    CPC classification number: G01R31/31713

    Abstract: A method of electrical testing electronic devices DUT, comprising: connecting at least an electronic device DUT to an automatic testing apparatus suitable for performing the testing of digital circuits or memories or of digital circuits and memories; sending electrical testing command signals to the electronic device DUT by means of the ATE apparatus; performing electrical testing of the electronic device DUT by means of at least one advanced supervised self testing system “Advanced Low Pin Count BIST” ALB which is built in the electronic device DUT, the ALB system being digitally interfaced with the ATE through a dedicated digital communication channel; and sending reply messages, if any, which comprise measures, failure information and reply data to the command signals from the electronic device DUT toward the ATE apparatus by means of the digital communication channel.

    Abstract translation: 一种电气测试电子设备DUT的方法，包括：至少将电子设备DUT连接到适于执行数字电路或存储器或数字电路和存储器的测试的自动测试设备; 通过ATE设备向电子设备DUT发送电测试命令信号; 通过至少一个高级监督自检系统“内置在电子设备DUT”中的“高级低引脚数BIST”ALB进行电子设备DUT的电气测试，ALB系统通过专用数字通信与ATE进行数字接口 渠道; 并且通过数字通信信道向电子设备DUT向ATE设备发送包括测量，故障信息和答复数据的回复消息（如果有的话）到命令信号。

    Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device
    10.
    发明授权
    Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device 有权
    用于控制测试探针在集成在半导体和相应的电子设备上的电子设备的终端上的正确定位的过程

    公开(公告)号：US09146273B2

    公开(公告)日：2015-09-29

    申请号：US12974957

    申请日：2010-12-21

    Applicant: Alberto Pagani

    Inventor： Alberto Pagani

    IPC: G01R31/00 ,  G01R31/28

    CPC classification number: G01R31/2884 ,  G01R31/2889 ,  G01R31/2891

    Abstract: An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.

    Abstract translation: 用于检查在晶片上执行的电气类型的实施例，用于测试探针卡的探针在集成在半导体晶片上的电子器件的焊盘或凸块上的正确定位或对准。 一个实施例在于使电流在上述装置中的至少一个的密封环的至少一部分中循环，并且在其必须在更多装置的密封环中流动的情况下，这些密封环适当地彼此互连。 由于实施例，密封环也可以在芯片的角度区域中被加强，并且合适的电路可能可能插入密封环中或密封环之间。

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