Invention Grant
US09148166B2 Adding predefined offset to coarse ADC residue output to SAR
有权
将预定义的偏移量添加到粗略的ADC残差输出到SAR
- Patent Title: Adding predefined offset to coarse ADC residue output to SAR
- Patent Title (中): 将预定义的偏移量添加到粗略的ADC残差输出到SAR
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Application No.: US14255269Application Date: 2014-04-17
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Publication No.: US09148166B2Publication Date: 2015-09-29
- Inventor: Subramanian Jagdish Narayan , Anand Kannan
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: H03M1/06
- IPC: H03M1/06 ; H03M1/38 ; H03M1/66

Abstract:
A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.
Public/Granted literature
- US20150188561A1 NOVEL TECHNIQUE TO COMBINE A COARSE ADC AND A SAR ADC Public/Granted day:2015-07-02
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