发明授权
US09166604B2 Timing monitor for PLL 有权
PLL定时监视器

Timing monitor for PLL
摘要:
Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.
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