A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (FDSOI) technology. By enhancing the performance of the NMOS and devices within the level shifting circuit, the Vt of the dual gate FDSOI NMOS transistors is lowered without a need for additional control circuitry. Lowering the Vt can be accomplished through dynamic secondary gate control, by coupling together primary and secondary gates of the NMOS devices, while secondary gates of the PMOS devices can be coupled to a high voltage supply level. Such high performance NMOS devices can then operate at higher frequencies and run on a much wider range of core power supplies. Meanwhile, conventional DC conditions are maintained during steady state operation. Because no components are added to the level shifter circuit, the higher performance is achieved without an increase in size and current consumption.