Invention Grant
- Patent Title: Stacked dual-chip packaging structure and preparation method thereof
- Patent Title (中): 堆叠双芯片封装结构及其制备方法
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Application No.: US13663694Application Date: 2012-10-30
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Publication No.: US09184117B2Publication Date: 2015-11-10
- Inventor: Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
- Applicant: Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
- Applicant Address: US CA Sunnyvale
- Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
- Current Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
- Current Assignee Address: US CA Sunnyvale
- Agent Chein-Hwa S. Tsao; Chen-Chi Lin
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/495 ; H01L23/31 ; H01L23/00 ; H01L21/683
Abstract:
The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.
Public/Granted literature
- US20140117523A1 STACKED DUAL-CHIP PACKAGING STRUCTURE AND PREPARATION METHOD THEREOF Public/Granted day:2014-05-01
Information query
IPC分类:
