公开(公告)号：US10770543B2

公开(公告)日：2020-09-08

申请号：US16191070

申请日：2018-11-14

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hideaki Tsuchiko

IPC分类号： H01L29/06 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/761 ,  H01L27/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/10 ,  H01L29/735 ,  H01L29/861 ,  H01L29/423

摘要： The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.

公开(公告)号：US10686056B2

公开(公告)日：2020-06-16

申请号：US15396384

申请日：2016-12-30

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yangping Ding ,  Sik Lui ,  Madhur Bobde ,  Lei Zhang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78

摘要： A semiconductor power device formed in a semiconductor substrate that includes a plurality of trenches formed at a top portion of the semiconductor substrate. The trenches extend laterally across the semiconductor substrate along a longitudinal direction and each trench has a nonlinear portion thus the nonlinear portion has a trench sidewall perpendicular to the longitudinal direction of the trench. A plurality of trench bottom dopant regions are formed below the trench bottom surface. A sidewall dopant region is formed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

公开(公告)号：US10680097B2

公开(公告)日：2020-06-09

申请号：US15699966

申请日：2017-09-08

申请人： Alpha and Omega Semiconductor Incorporated

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417

摘要： A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.

公开(公告)号：US10446545B2

公开(公告)日：2019-10-15

申请号：US15199828

申请日：2016-06-30

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Sik Lui

IPC分类号： H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/74 ,  H01L27/07

摘要： A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.

公开(公告)号：US10418899B2

公开(公告)日：2019-09-17

申请号：US14252568

申请日：2014-04-14

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Sik K. Lui ,  Daniel S. Ng ,  Xiaobin Wang

IPC分类号： H02M3/158 ,  H03K17/16

摘要： A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first threshold voltage and the second MOS transistor has a second threshold voltage where the first threshold voltage is less than the second threshold voltage.

公开(公告)号：US10325908B2

公开(公告)日：2019-06-18

申请号：US15498289

申请日：2017-04-26

申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

发明人： Sik Lui ,  Madhur Bobde ,  Ji Pan

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/167

摘要： A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a source contact extending to the body region formed in a source contact trench next to the gate trench. The lightly doped source region is extended deeper in the body region than the heavily doped source region. The lightly doped source region is adjacent to the source contact trench. A ballast resistor is formed at the lightly doped source region between the heavily doped source region and the body region and a Schottky diode is formed at a contact between the source contact and the lightly doped source region.

公开(公告)号：US10319848B2

公开(公告)日：2019-06-11

申请号：US16017686

申请日：2018-06-25

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hideaki Tsuchiko

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06

摘要： A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.

公开(公告)号：US10297594B2

公开(公告)日：2019-05-21

申请号：US14820482

申请日：2015-08-06

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

IPC分类号： H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

摘要： A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

公开(公告)号：US10199455B2

公开(公告)日：2019-02-05

申请号：US15600782

申请日：2017-05-21

申请人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

发明人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265

摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

公开(公告)号：US10177221B2

公开(公告)日：2019-01-08

申请号：US15878381

申请日：2018-01-23

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/872 ,  H01L29/10 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/51

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.