发明授权
- 专利标题： Stacked dual-chip packaging structure and preparation method thereof
- 专利标题（中）： 堆叠双芯片封装结构及其制备方法
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申请号： US13663694申请日： 2012-10-30
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公开(公告)号： US09184117B2公开(公告)日： 2015-11-10
- 发明人: Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
- 申请人： Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
- 申请人地址： US CA Sunnyvale
- 专利权人： ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
- 当前专利权人： ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
- 当前专利权人地址： US CA Sunnyvale
- 代理商 Chein-Hwa S. Tsao; Chen-Chi Lin
- 主分类号： H01L29/40
- IPC分类号： H01L29/40 ; H01L23/495 ; H01L23/31 ; H01L23/00 ; H01L21/683
摘要：
The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.
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