Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.