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公开(公告)号：US12265376B2
公开(公告)日：2025-04-01
申请号：US18055088
申请日：2022-11-14
Applicant: Analog Devices, Inc.
Inventor： John Kenney
IPC: H03K5/15 , G05B19/4155 , H03K3/037 , H03K5/00
Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.
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公开(公告)号：US11526153B2
公开(公告)日：2022-12-13
申请号：US17093311
申请日：2020-11-09
Applicant: Analog Devices, Inc.
Inventor： John Kenney
IPC: H03K3/37 , G05B19/4155 , H03K3/037 , H03K5/00
Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.
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公开(公告)号：US20140086364A1
公开(公告)日：2014-03-27
申请号：US13629170
申请日：2012-09-27
Applicant: ANALOG DEVICES, INC.
Inventor： Robert Schell , John Kenney , Wei-Hung Chen
CPC classification number: H03H7/06 , H03B27/00 , H03H7/20 , H03H7/21 , H03H11/22 , H03H2007/0192 , H04L7/0025 , H04L7/033
Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.
Abstract translation: 提供了正交时钟信号生成的装置和方法。 在某些实现中，正交时钟信号发生器包括正弦整形滤波器和多相滤波器。 正弦整形滤波器可以接收诸如正方形或矩形波的输入时钟信号，并且可以对输入时钟信号进行滤波以产生正弦时钟信号。 此外，多相滤波器可以使用正弦时钟信号来产生可以具有大约九十度的相位差的同相（I）和正交相（Q）时钟信号。 在某些配置中，由多相滤波器产生的同相和正交相位时钟信号可由缓冲电路缓冲，以产生适合在时钟和数据恢复中使用的同相和正交相位正弦参考时钟信号（CDR ）系统。
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公开(公告)号：US11711200B2
公开(公告)日：2023-07-25
申请号：US17644693
申请日：2021-12-16
Applicant: Analog Devices, Inc.
Inventor： Michael St. Germain , John Kenney
Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.
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公开(公告)号：US11509338B2
公开(公告)日：2022-11-22
申请号：US17204618
申请日：2021-03-17
Applicant: Analog Devices, Inc.
Inventor： John Kenney , Robert Schell , Rahul Vemuri
IPC: H04B1/12
Abstract: Systems and methods are provided for optimizing offset compensation in a receiver with multiple offset compensation D/A converters. At each stage where offset cancellation is applied, there is a fan-out of two or more. At the final stage, comparator offset compensation codes are summed and compared against a digital reference. In one version the digital reference is zero. A second implementation has a non-zero digital reference which is the sum of comparator offsets stored from start up. The difference between the sum of offsets and digital reference is applied to a digital accumulator. The most significant bits of the digital accumulator are applied to a digital D/A converter, which cancel analog offsets in an intermediate stage of amplifiers. The summation of offsets feeding into an accumulator is implemented for all preceding stages.
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Patent Agency Ranking
公开(公告)号：US08760209B2
公开(公告)日：2014-06-24
申请号：US13629170
申请日：2012-09-27
Applicant: Analog Devices, Inc.
Inventor： Robert Schell , John Kenney , Wei-Hung Chen
CPC classification number: H03H7/06 , H03B27/00 , H03H7/20 , H03H7/21 , H03H11/22 , H03H2007/0192 , H04L7/0025 , H04L7/033
Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.
Abstract translation: 提供了正交时钟信号生成的装置和方法。 在某些实现中，正交时钟信号发生器包括正弦整形滤波器和多相滤波器。 正弦整形滤波器可以接收诸如正方形或矩形波的输入时钟信号，并且可以对输入时钟信号进行滤波以产生正弦时钟信号。 此外，多相滤波器可以使用正弦时钟信号来产生可以具有大约九十度的相位差的同相（I）和正交相（Q）时钟信号。 在某些配置中，由多相滤波器产生的同相和正交相位时钟信号可由缓冲电路缓冲，以产生适合在时钟和数据恢复中使用的同相和正交相位正弦参考时钟信号（CDR ）系统。
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公开(公告)号：US12261608B2
公开(公告)日：2025-03-25
申请号：US18247691
申请日：2021-12-07
Applicant: Analog Devices, Inc.
Inventor： Hyman Shanan , John Kenney
Abstract: Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.
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公开(公告)号：US20230412175A1
公开(公告)日：2023-12-21
申请号：US18247691
申请日：2021-12-07
Applicant: Analog Devices, Inc.
Inventor： Hyman Shanan , John Kenney
CPC classification number: H03L7/099 , H03L1/02 , H03L7/189 , H04B1/16 , H03L2207/06
Abstract: Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.
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公开(公告)号：US20230198734A1
公开(公告)日：2023-06-22
申请号：US17644693
申请日：2021-12-16
Applicant: Analog Devices, Inc.
Inventor： Michael St. Germain , John Kenney
Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.
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公开(公告)号：US11303282B1
公开(公告)日：2022-04-12
申请号：US17382104
申请日：2021-07-21
Applicant: Analog Devices, Inc.
Inventor： John Kenney
Abstract: An apparatus is described and includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D/A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for computing a difference between a first state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a high voltage and a second state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a low voltage.
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