Invention Grant
US09190490B2 Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling
有权
用于垂直NAND性能增强和垂直缩放的局部掩埋沟道电介质
- Patent Title: Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling
- Patent Title (中): 用于垂直NAND性能增强和垂直缩放的局部掩埋沟道电介质
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Application No.: US13832721Application Date: 2013-03-15
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Publication No.: US09190490B2Publication Date: 2015-11-17
- Inventor: Randy J. Koval , Fatma A. Simsek-Ege
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L29/66 ; H01L29/78 ; H01L29/792 ; H01L27/115

Abstract:
A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.
Public/Granted literature
- US20140264527A1 LOCAL BURIED CHANNEL DIELECTRIC FOR VERTICAL NAND PERFORMANCE ENHANCEMENT AND VERTICAL SCALING Public/Granted day:2014-09-18
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