公开(公告)号：US09478643B2

公开(公告)日：2016-10-25

申请号：US14140215

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： John Hopkins ,  Fatma A. Simsek-Ege

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7889

Abstract: A memory structure having at least substantially aligned floating and control gates. Such a memory structure can include a control gate material disposed between a first insulator layer and a second insulator layer, a floating gate material disposed between the first insulator layer and the second insulator layer and at least substantially aligned with the control gate material, the floating gate material including a metal region, and an interpoly dielectric (IPD) layer disposed between the control gate material and the floating gate material such that the IPD layer electrically isolates the control gate material from the floating gate material.

Abstract translation: 一种具有至少基本对准的浮动和控制门的存储器结构。 这种存储器结构可以包括设置在第一绝缘体层和第二绝缘体层之间的控制栅极材料，设置在第一绝缘体层和第二绝缘体层之间并至少基本上与控制栅极材料对准的浮栅材料，浮动栅极材料 包括金属区域的栅极材料和设置在控制栅极材料和浮置栅极材料之间的多晶硅间电介质（IPD）层，使得IPD层将控制栅极材料与浮动栅极材料电隔离。

公开(公告)号：US09190490B2

公开(公告)日：2015-11-17

申请号：US13832721

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Randy J. Koval ,  Fatma A. Simsek-Ege

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7827 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7889 ,  H01L29/7926

Abstract: A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.

Abstract translation: 公开了一种用于形成非易失性存储器件的非易失性存储器件和方法。 存储器件利用NAND串中的局部掩埋沟道电介质，其减小了在NAND串的边缘处的体沟道泄漏，其中在编程操作期间沿串柱方向的电场梯度处于或接近最大值。 存储器件包括一端连接到位线的通道，另一端耦合到源极。 选择栅极形成在耦合到位线的通道的末端，以选择性地控制位线和通道之间的传导。 至少一个非易失性存储单元沿通道的长度在通道的选择栅极和第二端之间形成。 在通道的第一端处的通道内形成局部电介质区域。

公开(公告)号：US10141322B2

公开(公告)日：2018-11-27

申请号：US14109230

申请日：2013-12-17

Applicant: Intel Corporation

Inventor： Fatma A. Simsek-Ege ,  Nirmal Ramaswamy

IPC: H01L29/788 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11524

Abstract: A 3D NAND memory structure having improved process margin and enhanced performance is provided. Such a memory structure can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, a metal layer disposed between the control gate material and the floating gate material, an interpoly dielectric (IPD) layer disposed between the metal layer and the control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material coupled to the floating gate material opposite the control gate material.

公开(公告)号：US20160190313A1

公开(公告)日：2016-06-30

申请号：US14884210

申请日：2015-10-15

Applicant: Intel Corporation

Inventor： Randy J. Koval ,  Fatma A. Simsek-Ege

IPC: H01L29/78 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7889 ,  H01L29/7926

Abstract: A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.

Abstract translation: 公开了一种用于形成非易失性存储器件的非易失性存储器件和方法。 存储器件利用NAND串中的局部掩埋沟道电介质，其减小了在NAND串的边缘处的体沟道泄漏，其中在编程操作期间沿串柱方向的电场梯度处于或接近最大值。 存储器件包括一端连接到位线的通道，另一端耦合到源极。 选择栅极形成在耦合到位线的通道的末端，以选择性地控制位线和通道之间的传导。 至少一个非易失性存储单元沿通道的长度在通道的选择栅极和第二端之间形成。 在通道的第一端处的通道内形成局部电介质区域。

公开(公告)号：US10002767B2

公开(公告)日：2018-06-19

申请号：US15418618

申请日：2017-01-27

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Fatma A. Simsek-Ege

IPC: H01L27/115 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11558

Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.

公开(公告)号：US09722074B2

公开(公告)日：2017-08-01

申请号：US14884210

申请日：2015-10-15

Applicant: Intel Corporation

Inventor： Randy J. Koval ,  Fatma A. Simsek-Ege

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L29/7827 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7889 ,  H01L29/7926

Abstract: A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.