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US09195292B2 Controlling reduced power states using platform latency tolerance 有权
使用平台延迟容限来控制降低的功耗状态

Controlling reduced power states using platform latency tolerance
Abstract:
In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.
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