Invention Grant
US09195292B2 Controlling reduced power states using platform latency tolerance
有权
使用平台延迟容限来控制降低的功耗状态
- Patent Title: Controlling reduced power states using platform latency tolerance
- Patent Title (中): 使用平台延迟容限来控制降低的功耗状态
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Application No.: US13927746Application Date: 2013-06-26
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Publication No.: US09195292B2Publication Date: 2015-11-24
- Inventor: Barnes Cooper , Jeffrey R Wilcox , Michael N Derr , Neil W Songer , Craig S Forbell
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.
Public/Granted literature
- US20150006923A1 Controlling Reduced Power States Using Platform Latency Tolerance Public/Granted day:2015-01-01
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