Invention Grant
US09196334B2 Hierarchical memory magnetoresistive random-access memory (MRAM) architecture 有权
分层存储器磁阻随机存取存储器(MRAM)架构

Hierarchical memory magnetoresistive random-access memory (MRAM) architecture
Abstract:
A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second MTJ device having a second physical configuration. The first access latency is less than the second access latency.
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