Invention Grant
- Patent Title: Chip package and fabrication method thereof
- Patent Title (中): 芯片封装及其制造方法
-
Application No.: US14516492Application Date: 2014-10-16
-
Publication No.: US09196754B2Publication Date: 2015-11-24
- Inventor: Chia-Sheng Lin
- Applicant: XINTEC INC.
- Applicant Address: TW Taoyuan
- Assignee: XINTEC INC.
- Current Assignee: XINTEC INC.
- Current Assignee Address: TW Taoyuan
- Agency: Liu & Liu
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L31/02 ; H01L21/768 ; H01L23/31 ; H01L23/48 ; H01L23/525 ; H01L27/146 ; H01L31/0232 ; H01L31/18 ; H01L33/58 ; H01L33/62 ; H01L23/00

Abstract:
A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.
Public/Granted literature
- US20150035143A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF Public/Granted day:2015-02-05
Information query
IPC分类: