Invention Grant
US09209783B2 Efficient drift avoidance mechanism for synchronous and asynchronous digital sample rate converters
有权
用于同步和异步数字采样率转换器的高效漂移避免机制
- Patent Title: Efficient drift avoidance mechanism for synchronous and asynchronous digital sample rate converters
- Patent Title (中): 用于同步和异步数字采样率转换器的高效漂移避免机制
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Application No.: US14613388Application Date: 2015-02-04
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Publication No.: US09209783B2Publication Date: 2015-12-08
- Inventor: Yosef Bendel , Eyal Rosin , Assaf Ganor
- Applicant: DSP Group LTD.
- Applicant Address: IL Herzeliya
- Assignee: DSP GROUP LTD.
- Current Assignee: DSP GROUP LTD.
- Current Assignee Address: IL Herzeliya
- Agency: Reches Patents
- Main IPC: H03M7/00
- IPC: H03M7/00 ; H03H17/06 ; H04L27/26 ; G10L19/00 ; G10L21/04 ; H04L7/033 ; G10L19/008 ; H04L7/00

Abstract:
A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
Public/Granted literature
- US20150244349A1 Efficient Drift Avoidance Mechanism for Synchronous and asynchronous Digital Sample Rate Converters Public/Granted day:2015-08-27
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