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1.发明授权Efficient drift avoidance mechanism for synchronous and asynchronous digital sample rate converters 有权用于同步和异步数字采样率转换器的高效漂移避免机制公开(公告)号：US09209783B2
公开(公告)日：2015-12-08
申请号：US14613388
申请日：2015-02-04
Applicant: DSP Group LTD.
Inventor： Yosef Bendel , Eyal Rosin , Assaf Ganor
CPC classification number: H03H17/0657 , G06F5/06 , G10L19/00 , G10L19/008 , G10L21/04 , H03H17/0642 , H03H17/0664 , H03H17/0685 , H04L7/0037 , H04L7/033 , H04L7/0337 , H04L27/2657
Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
Abstract translation: 一种设备，包括第一内插器，其被配置为（a）以第一时钟速率接收具有第一采样率的第一信号，并且（b）以第二时钟速率输出具有第一期望采样的第二信号 速率平均 其中所述第一内插器包括：用于存储所述第一信号的第一缓冲器; 以及第一分数采样比电路，其被配置为产生固定点值的第一图案，其中所述第一图案的平均值对应于所述第一期望采样率平均值与所述第一采样率之间的第一期望采样率比。
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2.发明申请Efficient Drift Avoidance Mechanism for Synchronous and asynchronous Digital Sample Rate Converters 有权用于同步和异步数字采样率转换器的高效漂移避免机制公开(公告)号：US20150244349A1
公开(公告)日：2015-08-27
申请号：US14613388
申请日：2015-02-04
Applicant: DSP Group LTD.
Inventor： Yosef Bendel , Eyal Rosin , Assaf Ganor
IPC: H03H17/06
CPC classification number: H03H17/0657 , G06F5/06 , G10L19/00 , G10L19/008 , G10L21/04 , H03H17/0642 , H03H17/0664 , H03H17/0685 , H04L7/0037 , H04L7/033 , H04L7/0337 , H04L27/2657
Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
Abstract translation: 一种设备，包括第一内插器，其被配置为（a）以第一时钟速率接收具有第一采样率的第一信号，并且（b）以第二时钟速率输出具有第一期望采样的第二信号 速率平均 其中所述第一内插器包括：用于存储所述第一信号的第一缓冲器; 以及第一分数采样比电路，其被配置为产生固定点值的第一图案，其中所述第一图案的平均值对应于所述第一期望采样率平均值与所述第一采样率之间的第一期望采样率比。
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