发明授权
US09209962B1 High-speed clock skew correction for serdes receivers 有权
针对serdes接收机的高速时钟偏移校正

High-speed clock skew correction for serdes receivers
摘要:
The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.
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