发明授权
US09210809B2 Reduced PTH pad for enabling core routing and substrate layer count reduction
有权
减少PTH焊盘，使核心布线和基板层数减少
- 专利标题： Reduced PTH pad for enabling core routing and substrate layer count reduction
- 专利标题（中）： 减少PTH焊盘，使核心布线和基板层数减少
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申请号： US14097932申请日： 2013-12-05
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公开(公告)号： US09210809B2公开(公告)日： 2015-12-08
- 发明人: Debendra Mallik , Mihir Roy
- 申请人： Debendra Mallik , Mihir Roy
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Winkle, PLLC
- 主分类号： H01L23/52
- IPC分类号： H01L23/52 ; H01L23/48 ; H05K1/11 ; H01L21/48 ; H01L23/498
摘要：
Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
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