Invention Grant
- Patent Title: Memory architecture of thin film 3D array
- Patent Title (中): 薄膜3D阵列的内存架构
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Application No.: US13970482Application Date: 2013-08-19
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Publication No.: US09214351B2Publication Date: 2015-12-15
- Inventor: Yi-Hsuan Hsiao , Hang-Ting Lue , Wei-Chen Chen
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L21/28 ; H01L29/792 ; H01L27/115 ; G11C16/34 ; G11C16/10 ; G11C16/26

Abstract:
A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.
Public/Granted literature
- US20140269078A1 MEMORY ARCHITECTURE OF THIN FILM 3D ARRAY Public/Granted day:2014-09-18
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