Invention Grant
- Patent Title: Reduced bitcount polygon rasterization
- Patent Title (中): 减少位数多边形光栅化
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Application No.: US13647071Application Date: 2012-10-08
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Publication No.: US09218679B2Publication Date: 2015-12-22
- Inventor: Jacob Subag , Nir Benty
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T11/40 ; G06T15/10

Abstract:
Techniques are disclosed for carrying out rasterization of a given graphics workload, wherein portions of the workload associated with relatively high bit count operations are processed via a first process path, and portions of the workload associated with relatively lower bit count operations are processed via a second, relatively faster process path, in accordance with an embodiment. In a more general sense, maximal bit count associated with a given primitive can be identified and compared to a threshold to determine which one of multiple available processing paths can be used.
Public/Granted literature
- US20140098084A1 REDUCED BITCOUNT POLYGON RASTERIZATION Public/Granted day:2014-04-10
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |