Invention Grant
US09223715B2 Microprocessor mechanism for decompression of cache correction data
有权
用于解压缩缓存校正数据的微处理器机制
- Patent Title: Microprocessor mechanism for decompression of cache correction data
- Patent Title (中): 用于解压缩缓存校正数据的微处理器机制
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Application No.: US13972785Application Date: 2013-08-21
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Publication No.: US09223715B2Publication Date: 2015-12-29
- Inventor: G. Glenn Henry , Dinesh K. Jain
- Applicant: VIA TECHNOLOGIES, INC.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee Address: CN Shanghai
- Agent Richard K. Huffman; James W. Huffman
- Main IPC: G06F13/12
- IPC: G06F13/12 ; G11C17/18 ; G11C7/00 ; G11C8/00 ; G06F12/08 ; G11C17/16 ; G06F3/06 ; G06F9/44 ; G06F9/445 ; G06F12/06 ; G11C29/00 ; G06F11/10

Abstract:
An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.
Public/Granted literature
- US20150055428A1 MICROPROCESSOR MECHANISM FOR DECOMPRESSION OF CACHE CORRECTION DATA Public/Granted day:2015-02-26
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