公开(公告)号：US10423216B2

公开(公告)日：2019-09-24

申请号：US14077740

申请日：2013-11-12

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Terry Parks ,  G. Glenn Henry

IPC: G06F9/46 ,  G06F1/3293 ,  G06F9/50

Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

公开(公告)号：US10409347B2

公开(公告)日：2019-09-10

申请号：US16191691

申请日：2018-11-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Darius D. Gaskins

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/24 ,  G06F13/36 ,  G06F15/163 ,  G06F9/30 ,  G06F9/50 ,  G06F9/445 ,  G06F15/82 ,  G06F1/3234 ,  G06F11/36 ,  G06F11/14

Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

公开(公告)号：US20190107873A1

公开(公告)日：2019-04-11

申请号：US16191691

申请日：2018-11-15

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Darius D. Gaskins

IPC: G06F1/26 ,  G06F1/24 ,  G06F13/36 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30 ,  G06F15/82 ,  G06F15/163 ,  G06F9/50 ,  G06F9/445

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

公开(公告)号：US10216520B2

公开(公告)日：2019-02-26

申请号：US14569313

申请日：2014-12-12

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Matthew Daniel Day ,  G. Glenn Henry ,  Terry Parks

IPC: G06F9/38

Abstract: A compressing instruction queue for a microprocessor including a storage queue and a redirect logic circuit. The storage queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic circuit is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the storage queue without leaving unused storage locations and beginning at a first available storage location in the storage queue. The redirect logic circuit performs redirection and compression to eliminate empty locations or holes in the storage queue and to reduce the number of write ports interfaced with each storage location of the storage queue.

公开(公告)号：US09798898B2

公开(公告)日：2017-10-24

申请号：US14884525

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/00 ,  G06F21/72 ,  G06F9/30 ,  H04L9/08 ,  G06F21/74 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/60 ,  G06F21/71 ,  H04L9/06

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0827 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor conditionally grants a request to switch from a normal execution mode in which encrypted instructions cannot be executed, into a secure execution mode (SEM). Thereafter, the microprocessor executes a plurality of instructions, including a store-key instruction to write a set of one or more cryptographic key values into a secure memory of the microprocessor. After fetching an encrypted program from an instruction cache, the microprocessor decrypts the encrypted program into plaintext instructions using decryption logic within the microprocessor's instruction-processing pipeline.

公开(公告)号：US09575541B2

公开(公告)日：2017-02-21

申请号：US14281796

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F15/16 ,  G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

Abstract translation: 一种微处理器，多个处理核心，其中所述多个处理核心中的每一个都实例化相应的体系结构可视存储资源。 多个处理核心的第一核心被配置为遇到指令第一核心以由架构指令指定的值来更新第一核心的各个架构可见存储资源的架构指令。 第一核还被配置为响应于遇到结构指令而向多个处理核心中的另一个处理核心中的每一个提供该值，并用该值来更新第一核心的相应的架构可见存储资源。 除了第一核心之外的多个处理核心的每个核心被配置为利用由第一核心提供的值来更新核心的各个体系结构可见的存储资源，而不会遇到建筑指令。

公开(公告)号：US09367497B2

公开(公告)日：2016-06-14

申请号：US14522931

申请日：2014-10-24

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F13/36 ,  G06F15/163 ,  G06F1/32 ,  G06F1/24 ,  G06F9/30 ,  G06F9/50 ,  G06F9/445 ,  G06F15/82 ,  G06F11/36 ,  G06F11/14

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Abstract translation: 一种用于动态重新配置多核微处理器的一个或多个核心的方法，所述多核微处理器包括多个核心和边带通信线路，其外部连接到连接到芯片组的系统总线，这有助于非系统总线核心间通信。 为了构建基于边带的核心间通信的目的，至少一些核可操作以可重新配置地指定或不具有主凭证。 该方法包括确定微处理器的核心的初始配置，该配置指定至少一个核心，但不将所有核心指定为主核心，并且根据修改的配置重新配置核心，该修改的配置删除主命名 从最初如此指定的核心，并将主指定分配给最初未指定的核心。 每个核心被配置为基于其指定或不存在作为主核心有条件地驱动其所连接的边带通信线。

公开(公告)号：US20150134978A1

公开(公告)日：2015-05-14

申请号：US14079299

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572

Abstract: An apparatus including a ROM, a selector, and a detector. The ROM has a partitions, each stored as plaintext, and a encrypted digests, each comprising an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more partitions responsive to an interrupt. The detector generates the interrupt at a combination of intervals and event occurrences, and accesses the one or more partitions and corresponding one or more encrypted digests upon assertion of the interrupt, and directs a microprocessor to generate corresponding one or more second digests corresponding to the one or more partitions and corresponding one or more decrypted digests corresponding to the one or more encrypted digests using the same algorithms and key that were employed to generate the first message digest and encrypted digests, and compares the one or more second digests with the one or more decrypted digests, and precludes the operation if the one or more second digests and the one or more decrypted digests are not pair wise equal.

Abstract translation: 一种包括ROM，选择器和检测器的装置。 ROM具有每个存储为明文的分区和加密的摘要，每个分组包括与相应的一个分区相关联的第一摘要的加密版本。 选择器响应于中断选择一个或多个分区。 检测器以间隔和事件发生的组合生成中断，并且在断言中访问一个或多个分区和相应的一个或多个加密摘要，并指示微处理器产生对应于该中断的对应的一个或多个第二摘要 或更多分区和对应于使用与生成第一消息摘要和加密摘要相同的算法和密钥的一个或多个加密摘要的对应的一个或多个解密摘要，并将该一个或多个第二摘要与一个或多个 解密的摘要，并且如果一个或多个第二摘要和一个或多个解密的摘要不是成对相等的，则排除操作。

公开(公告)号：US20150134976A1

公开(公告)日：2015-05-14

申请号：US14079145

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/06 ,  H04L9/0618 ,  H04L9/0869 ,  H04L9/3231 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0876 ,  H04L63/123

Abstract: An apparatus including a ROM, an event detector, and a tamper detector. The ROM has BIOS contents stored as plaintext, and an encrypted digest. The encrypted digest is an encrypted version of a first digest corresponding to the BIOS contents. The event detector generates an interrupt that interrupts operation of the system upon occurrence of an event. The tamper detector is operatively coupled to the ROM and accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs a microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second digest and the decrypted digest are not equal.

Abstract translation: 一种包括ROM，事件检测器和篡改检测器的装置。 ROM具有存储为明文的BIOS内容和加密摘要。 加密摘要是对应于BIOS内容的第一摘要的加密版本。 事件检测器产生中断事件发生时系统的操作。 篡改检测器可操作地耦合到ROM，并且在断言中访问BIOS内容和加密的摘要，并引导微处理器生成对应于BIOS内容的第二摘要和对应于加密摘要的解密摘要 用于生成第一摘要和加密摘要的算法和密钥，并将第二消息摘要与解密的消息摘要进行比较，并且如果第二摘要和解密的摘要不相等，则排除微处理器的操作。

公开(公告)号：US20150067369A1

公开(公告)日：2015-03-05

申请号：US14281434

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F1/04 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/04 ,  G06F1/32 ,  G06F9/522 ,  G06F12/0891 ,  G06F2212/1028 ,  G06F2212/60

Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

Abstract translation: 微处理器包括控制单元，该控制单元被配置为选择性地将各个时钟信号控制到多个处理核心中的每一个。 每个处理核心被配置为分别向控制单元写入一个值。 对于所述多个处理核心的每个核心，所述控制单元被配置为响应于所述核心向所述控制单元写入值而将相应的时钟信号关断到所述核心。 控制单元被配置为检测当所有处理核心已经向控制单元写入值并且控制单元已经将各个时钟信号截止到所有处理核心时发生的状况。 控制单元被配置为响应于检测到所发生的状况，同时将各个时钟信号接通到所有处理核心。