公开(公告)号：US20150054543A1

公开(公告)日：2015-02-26

申请号：US13972690

申请日：2013-08-21

Applicant: Via Technologies, Inc.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F15/7807

Abstract: An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data.

Abstract translation: 一种装置包括熔丝阵列，随机存取存储器（RAM）和多个核。 熔丝阵列设置在管芯上，其中熔丝阵列具有多个半导体保险丝，其被编程有压缩的配置数据。 RAM分开设置在模具上。 多个芯分别设置在管芯上，其中多个芯中的每个芯耦合到熔丝阵列和RAM，并且其中多个芯中的每一个在上电/下电时访问熔丝阵列或RAM， 由负载数据寄存器的内容指示复位以获得压缩的配置数据。

公开(公告)号：US20150058695A1

公开(公告)日：2015-02-26

申请号：US13972812

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G06F11/10 ,  H03M7/702 ,  H03M13/05

Abstract: An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

Abstract translation: 一种装置具有共享熔丝阵列和多个微处理器核心。 共享保险丝阵列设置在管芯上，共享保险丝阵列具有多个半导体保险丝，其编程有压缩配置数据和错误校验（ECC）代码。 多个微处理器核心设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化 多个核心中的每一个。 所述多个核心中的每一个包括复位控制器，其被配置为访问所述压缩配置数据和所述ECC代码，以校正导致校正的压缩配置数据的错误，以解压缩所有经校正的压缩配置数据，并且分发解压缩配置 数据初始化元素。

公开(公告)号：US20150058564A1

公开(公告)日：2015-02-26

申请号：US13972481

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1008 ,  G06F15/76 ,  G11C29/787 ,  G11C29/802

Abstract: An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

Abstract translation: 一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核。 半导体熔丝阵列设置在芯片上，其中编程了配置数据。 半导体熔丝阵列具有第一多个半导体熔丝，其被配置为存储压缩的高速缓存校正数据。 高速缓冲存储器设置在管芯上。 多个芯设置在管芯上，其中多个芯中的每个芯耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在上电/复位时访问半导体熔丝阵列，以解压缩压缩高速缓存 校正数据，并且分发解压缩的缓存校正数据以初始化高速缓冲存储器。

公开(公告)号：US20150055428A1

公开(公告)日：2015-02-26

申请号：US13972785

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G06F12/0875 ,  G06F1/24 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0638 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/44505 ,  G06F11/1008 ,  G06F11/1068 ,  G06F12/0646 ,  G06F12/0692 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/1012 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/453 ,  G06F2212/601 ,  G06F2212/62 ,  G06F2212/69 ,  G11C17/16 ,  G11C17/18 ,  G11C29/52 ,  G11C29/802

Abstract: An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.

Abstract translation: 一种装置具有熔丝阵列，高速缓冲存储器和核心。 熔丝阵列设置在芯片上，其中编程了配置数据。 熔丝阵列包括第一多个保险丝和第二多个保险丝。 第一组多个保险丝存储压缩缓存校正数据。 第二多个保险丝存储压缩的熔丝校正数据，该数据指示与其先前存储的状态将改变其状态的第一组多个保险丝内的一个或多个保险丝对应的位置和值。 磁芯设置在芯片上，其中每个磁芯在上电/复位时访问熔丝阵列。 每个核心包括高速缓存熔丝解压缩器，其根据位置和值改变状态，解压缩压缩高速缓存校正数据，并分配解压缩的高速缓存校正数据以初始化高速缓冲存储器。

公开(公告)号：US20150058610A1

公开(公告)日：2015-02-26

申请号：US13972657

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F9/44

CPC classification number: G06F9/4403

Abstract: An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.

公开(公告)号：US20150058565A1

公开(公告)日：2015-02-26

申请号：US13972741

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F3/06 ,  G11C17/16

CPC classification number: G06F15/177 ,  G11C17/16 ,  G11C29/785

Abstract: An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.

公开(公告)号：US20150058563A1

公开(公告)日：2015-02-26

申请号：US13972358

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F3/06 ,  G11C17/16 ,  G06F12/08

CPC classification number: G06F15/177 ,  G06F12/0802 ,  G11C17/16 ,  G11C29/785

Abstract: An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

Abstract translation: 设想用于在多核微处理器中存储和解压缩配置数据的装置。 该装置包括共享熔丝阵列和多个微处理器核。 共享保险丝阵列设置在管芯上并且包括用压缩配置数据编程的多个半导体保险丝。 多个微处理器核心也设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化内部的元件 多个核心中的每一个。 多个核心中的每一个具有复位控制器，其被配置为解压缩所有压缩的配置数据，并且分发解压缩的配置数据以初始化元件。

公开(公告)号：US09348690B2

公开(公告)日：2016-05-24

申请号：US13972812

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F11/10 ,  H03M13/05 ,  H03M7/30

CPC classification number: G06F11/10 ,  H03M7/702 ,  H03M13/05

Abstract: An apparatus has a shared fuse array and a plurality of x86-compatible microprocessors disposed on a die. The shared fuse array has a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes accessible by a plurality of x86-compatible microprocessors and another plurality of semiconductor fuses programmed with uncompressed system hardware configuration data that is employed to initialize control circuit elements within the plurality of x86-compatible microprocessors. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessors is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of microprocessors. The each of the plurality of microprocessors includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors in said compressed configuration data resulting in corrected compressed configuration data, to decompress the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

Abstract translation: 一种装置具有共享熔丝阵列和设置在管芯上的多个x86兼容的微处理器。 共享熔丝阵列具有多个半导体熔丝，其编程有压缩配置数据，并且可由多个x86兼容微处理器访问的错误校验和校正（ECC）代码以及用未压缩系统硬件配置数据编程的另一多个半导体熔丝， 初始化多个x86兼容微处理器内的控制电路元件。 多个微处理器核心设置在管芯上，其中多个微处理器中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化每个 的多个微处理器。 所述多个微处理器中的每一个包括复位控制器，其被配置为访问所述压缩配置数据和所述ECC代码，以校正导致校正的压缩配置数据的所述压缩配置数据中的错误，以解压缩所述经校正的压缩配置数据，以及 分发解压缩的配置数据来初始化元素。

公开(公告)号：US09223715B2

公开(公告)日：2015-12-29

申请号：US13972785

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F13/12 ,  G11C17/18 ,  G11C7/00 ,  G11C8/00 ,  G06F12/08 ,  G11C17/16 ,  G06F3/06 ,  G06F9/44 ,  G06F9/445 ,  G06F12/06 ,  G11C29/00 ,  G06F11/10

CPC classification number: G06F12/0875 ,  G06F1/24 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0638 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/44505 ,  G06F11/1008 ,  G06F11/1068 ,  G06F12/0646 ,  G06F12/0692 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/1012 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/453 ,  G06F2212/601 ,  G06F2212/62 ,  G06F2212/69 ,  G11C17/16 ,  G11C17/18 ,  G11C29/52 ,  G11C29/802

Abstract: An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.

Abstract translation: 一种装置具有熔丝阵列，高速缓冲存储器和核心。 熔丝阵列设置在芯片上，其中编程了配置数据。 熔丝阵列包括第一多个保险丝和第二多个保险丝。 第一组多个保险丝存储压缩缓存校正数据。 第二多个保险丝存储压缩的熔丝校正数据，该数据指示与其先前存储的状态将改变其状态的第一组多个保险丝内的一个或多个保险丝对应的位置和值。 磁芯设置在芯片上，其中每个磁芯在上电/复位时访问熔丝阵列。 每个核心包括高速缓存熔丝解压缩器，其根据位置和值改变状态，解压缩压缩高速缓存校正数据，并且分配解压缩的高速缓存校正数据以初始化高速缓冲存储器。

公开(公告)号：US20150058609A1

公开(公告)日：2015-02-26

申请号：US13972297

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F9/44

CPC classification number: G06F9/4403 ,  G06F9/4405 ,  G06F15/177 ,  G06F15/76

Abstract: An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract translation: 一种装置包括多个芯和一个熔丝阵列。 多个芯设置在模具上。 熔丝阵列设置在管芯上，并且耦合到多个芯中的每一个，其中熔丝阵列包括多个半导体熔丝，所述多个半导体熔丝用多个芯中的每一个的压缩配置数据进行编程， 多个核在加电/复位时访问和解压缩所有压缩的配置数据，以用于初始化多个核心内的元件。