Invention Grant
US09224474B2 P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals
有权
P通道3D存储器阵列以及利用带对频带和fowler-nordheim隧道原理在比特级和块级别对其进行编程和擦除的方法
- Patent Title: P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals
- Patent Title (中): P通道3D存储器阵列以及利用带对频带和fowler-nordheim隧道原理在比特级和块级别对其进行编程和擦除的方法
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Application No.: US14019183Application Date: 2013-09-05
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Publication No.: US09224474B2Publication Date: 2015-12-29
- Inventor: Hang-Ting Lue
- Applicant: Macronix International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/10 ; G11C16/34 ; H01L27/115
Abstract:
A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce −FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce −FN hole tunneling in selected blocks of cells.
Public/Granted literature
- US20140192594A1 P-CHANNEL 3D MEMORY ARRAY Public/Granted day:2014-07-10
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