Invention Grant
- Patent Title: Dual epitaxy region integration
- Patent Title (中): 双重外延区域整合
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Application No.: US14029896Application Date: 2013-09-18
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Publication No.: US09224607B2Publication Date: 2015-12-29
- Inventor: Kangguo Cheng , Ali Khakifirooz , Shom Ponoth , Raghavasimhan Sreenivasan
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent David Cain; Andrew M. Calderon
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L21/28 ; H01L21/8238 ; H01L21/84 ; H01L27/092 ; H01L29/66 ; H01L21/02
Abstract:
A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region.
Public/Granted literature
- US20150076608A1 DUAL EPITAXY REGION INTEGRATION Public/Granted day:2015-03-19
Information query
IPC分类:
