Hard mask for source/drain epitaxy control

Invention Grant

US09224657B2 Hard mask for source/drain epitaxy control 有权

Title translation: 用于源极/漏极外延控制的硬掩模

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Patent Title: Hard mask for source/drain epitaxy control
Patent Title (中): 用于源极/漏极外延控制的硬掩模
Application No.: US13960517

Application Date: 2013-08-06
Publication No.: US09224657B2

Publication Date: 2015-12-29
Inventor: David Gerald Farber , Tom Lii , Brian K. Kirkpatrick
Applicant: Texas Instruments Incorporated
Applicant Address: US TX Dallas
Assignee: TEXAS INSTRUMENTS INCORPORATED
Current Assignee: TEXAS INSTRUMENTS INCORPORATED
Current Assignee Address: US TX Dallas
Agent Jacqueline J. Garner; Frank D. Cimino
Main IPC: H01L21/8238
IPC: H01L21/8238

Hard mask for source/drain epitaxy control

Abstract:

An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract(Chinese):

集成电路形成为包括第一极性MOS晶体管和第二相反极性MOS晶体管。在第一极性MOS晶体管和第二极性MOS晶体管上形成具有1原子％至30原子％硅的硅掺杂氮化硼（SixBN）的硬掩模。硬掩模从第一极性MOS晶体管的源极/漏极区域移除，并且在第二极性MOS晶体管上保持原位。半导体材料在第一极性MOS晶体管的源极/漏极区域外延生长，同时硬掩模就位。随后，从第二极性MOS晶体管去除硬掩模。

Public/Granted literature

US20150044830A1 HARD MASK FOR SOURCE/DRAIN EPITAXY CONTROL Public/Granted day:2015-02-12

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS