发明授权
- 专利标题： Adjustable buffer circuit
- 专利标题（中）： 可调缓冲电路
-
申请号： US14681898申请日： 2015-04-08
-
公开(公告)号： US09225332B1公开(公告)日： 2015-12-29
- 发明人: Wenfeng Zhang , Parag Upadhyaya
- 申请人： Xilinx, Inc.
- 申请人地址： US CA San Jose
- 专利权人： XILINX, INC.
- 当前专利权人： XILINX, INC.
- 当前专利权人地址： US CA San Jose
- 代理商 LeRoy D. Maunu
- 主分类号： H03K19/094
- IPC分类号： H03K19/094 ; H03K19/0185
摘要：
A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.
信息查询
IPC分类:
