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公开(公告)号：US11695397B2
公开(公告)日：2023-07-04
申请号：US17398675
申请日：2021-08-10
申请人： XILINX, INC.
发明人： Wenfeng Zhang , Parag Upadhyaya
摘要： Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.
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公开(公告)号：US20170134009A1
公开(公告)日：2017-05-11
申请号：US14933346
申请日：2015-11-05
申请人： Xilinx, Inc.
发明人： Jinyung Namkoong , Wenfeng Zhang , Parag Upadhyaya
IPC分类号： H03K3/01
CPC分类号： H03K3/01 , H03K19/017527
摘要： Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.
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公开(公告)号：US09225332B1
公开(公告)日：2015-12-29
申请号：US14681898
申请日：2015-04-08
申请人： Xilinx, Inc.
发明人： Wenfeng Zhang , Parag Upadhyaya
IPC分类号： H03K19/094 , H03K19/0185
CPC分类号： H03K19/018514 , H03K19/09432
摘要： A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.
摘要翻译： 共模逻辑缓冲器件包括被配置为提供源极电流的电流源。 输入级包括第一MOS晶体管对，其被配置为从源电流和基于输入差分电压产生两个输出路径之间的差分电流。 输出级包括被配置为基于为两个输出路径中的每一个提供的有效阻抗产生输出差分电压的第二MOS晶体管对。 调整电路被配置为响应于控制信号调整第二MOS晶体管对的有效阻抗。
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公开(公告)号：US09774315B2
公开(公告)日：2017-09-26
申请号：US14933346
申请日：2015-11-05
申请人： Xilinx, Inc.
发明人： Jinyung Namkoong , Wenfeng Zhang , Parag Upadhyaya
CPC分类号： H03K3/01 , H03K19/017527
摘要： Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.
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公开(公告)号：US11575497B2
公开(公告)日：2023-02-07
申请号：US17351028
申请日：2021-06-17
申请人： XILINX, INC.
摘要： In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.
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公开(公告)号：US10715358B1
公开(公告)日：2020-07-14
申请号：US16205020
申请日：2018-11-29
申请人： Xilinx, Inc.
发明人： Wenfeng Zhang , Stanley Y. Chen , Hsung Jai Im , Parag Upadhyaya
IPC分类号： H04L25/03
摘要： A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.
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