Invention Grant
- Patent Title: Enhanced dislocation stress transistor
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Application No.: US14582391Application Date: 2014-12-24
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Publication No.: US09231076B2Publication Date: 2016-01-05
- Inventor: Cory E. Weber , Mark Y. Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kathy J. Ortiz
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L31/0312 ; H01L29/66 ; H01L21/265 ; H01L29/417 ; H01L29/78 ; H01L29/16
Abstract:
A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
Public/Granted literature
- US20150155384A1 ENHANCED DISLOCATION STRESS TRANSISTOR Public/Granted day:2015-06-04
Information query
IPC分类:
