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公开(公告)号:US10651093B2
公开(公告)日:2020-05-12
申请号:US16020722
申请日:2018-06-27
Applicant: Intel Corporation
Inventor: Srijit Mukherjee , Christopher J. Wiegand , Tyler J. Weeks , Mark Y. Liu , Michael L. Hattendorf
IPC: H01L29/49 , H01L21/8238 , H01L27/088 , H01L29/66 , H01L27/11 , H01L27/092 , H01L21/8234 , H01L21/28
Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
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公开(公告)号:US20170222052A1
公开(公告)日:2017-08-03
申请号:US15489423
申请日:2017-04-17
Applicant: Intel Corporation
Inventor: Cory E. Weber , Mark Y. Liu , Anand S. Murthy , Hemant V. Deshpande , Daniel B. Aubertine
IPC: H01L29/78 , H01L29/08 , H01L29/66 , H01L29/16 , H01L29/417 , H01L21/265 , H01L29/165
CPC classification number: H01L29/7848 , H01L21/26506 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/66477 , H01L29/66628 , H01L29/78 , H01L29/7847 , H01L29/7849
Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
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公开(公告)号:US11664452B2
公开(公告)日:2023-05-30
申请号:US17085981
申请日:2020-10-30
Applicant: Intel Corporation
Inventor: Pratik A. Patel , Mark Y. Liu , Jami A. Wiedemer , Paul A. Packan
IPC: H01L29/78 , H01L29/66 , H01L21/225 , H01L21/324 , H01L29/08 , H01L29/24 , H01L29/267
CPC classification number: H01L29/7848 , H01L21/2253 , H01L21/324 , H01L29/0847 , H01L29/24 , H01L29/267 , H01L29/66492 , H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/785 , H01L29/7851
Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.
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公开(公告)号:US11183432B2
公开(公告)日:2021-11-23
申请号:US16844588
申请日:2020-04-09
Applicant: Intel Corporation
Inventor: Srijit Mukherjee , Christopher J. Wiegand , Tyler J. Weeks , Mark Y. Liu , Michael L. Hattendorf
IPC: H01L27/092 , H01L21/8238 , H01L27/088 , H01L29/66 , H01L27/11 , H01L21/8234 , H01L21/28 , H01L29/49
Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
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公开(公告)号:US09231076B2
公开(公告)日:2016-01-05
申请号:US14582391
申请日:2014-12-24
Applicant: Intel Corporation
Inventor: Cory E. Weber , Mark Y. Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
IPC: H01L29/15 , H01L31/0312 , H01L29/66 , H01L21/265 , H01L29/417 , H01L29/78 , H01L29/16
CPC classification number: H01L29/7848 , H01L21/26506 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/66477 , H01L29/66628 , H01L29/78 , H01L29/7847 , H01L29/7849
Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
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公开(公告)号:US12165928B2
公开(公告)日:2024-12-10
申请号:US17505468
申请日:2021-10-19
Applicant: Intel Corporation
Inventor: Srijit Mukherjee , Christopher J. Wiegand , Tyler J. Weeks , Mark Y. Liu , Michael L Hattendorf
IPC: H01L29/66 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/49 , H10B10/00
Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
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公开(公告)号:US11387320B2
公开(公告)日:2022-07-12
申请号:US16707490
申请日:2019-12-09
Applicant: INTEL CORPORATION
Inventor: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC: H01L29/06 , H01L21/285 , H01L29/165 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/78 , H01L29/423 , H01L21/768 , H01L29/167 , H01L21/02 , H01L29/08 , H01L29/36 , H01L27/092 , H01L23/535 , H01L29/417 , H01L21/3215 , H01L29/778
Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
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公开(公告)号:US10084087B2
公开(公告)日:2018-09-25
申请号:US15489423
申请日:2017-04-17
Applicant: Intel Corporation
Inventor: Cory E. Weber , Mark Y. Liu , Anand S. Murthy , Hemant V. Deshpande , Daniel B. Aubertine
IPC: H01L29/78 , H01L21/265 , H01L29/08 , H01L29/165 , H01L29/16 , H01L29/417 , H01L29/66
CPC classification number: H01L29/7848 , H01L21/26506 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/66477 , H01L29/66628 , H01L29/78 , H01L29/7847 , H01L29/7849
Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
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公开(公告)号:US09627384B2
公开(公告)日:2017-04-18
申请号:US14535387
申请日:2014-11-07
Applicant: Intel Corporation
Inventor: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC: H01L29/66 , H01L27/092 , H01L21/285 , H01L29/165 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/167 , H01L21/02 , H01L29/08 , H01L29/36
CPC classification number: H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
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10.
公开(公告)号:US09418898B2
公开(公告)日:2016-08-16
申请号:US14548215
申请日:2014-11-19
Applicant: Intel Corporation
Inventor: Srijit Mukherjee , Christopher J. Wiegand , Tyler J Weeks , Mark Y. Liu , Michael L. Hattendorf
IPC: H01L27/088 , H01L21/8234 , H01L29/66 , H01L27/092 , H01L21/28 , H01L27/11 , H01L21/8238
CPC classification number: H01L21/82385 , H01L21/28008 , H01L21/823431 , H01L21/823456 , H01L21/823821 , H01L27/088 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L29/495 , H01L29/66477
Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中,模拟电路采用具有给定z高度的栅电极的晶体管,而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中,基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。
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