Invention Grant
- Patent Title: Graphene transistor with a sublithographic channel width
- Patent Title (中): 具有亚光刻通道宽度的石墨烯晶体管
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Application No.: US14181832Application Date: 2014-02-17
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Publication No.: US09236477B2Publication Date: 2016-01-12
- Inventor: Jack O. Chu , Christos Dimitrakopoulos , Eric C. Harley , Judson R. Holt , Timothy J. McArdle , Matthew W. Stoker
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/16 ; H01L21/02 ; H01L21/324 ; H01L29/66 ; H01L29/06

Abstract:
Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion.
Public/Granted literature
- US20150236147A1 GRAPHENE TRANSISTOR WITH A SUBLITHOGRAPHIC CHANNEL WIDTH Public/Granted day:2015-08-20
Information query
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