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    Partial FIN on oxide for improved electrical isolation of raised active regions
    1.
    发明授权
    Partial FIN on oxide for improved electrical isolation of raised active regions 有权
    氧化物部分FIN，用于改善凸起活性区域的电气隔离

    公开(公告)号：US09219114B2

    公开(公告)日：2015-12-22

    申请号：US13940280

    申请日：2013-07-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

    Abstract: A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

    Abstract translation: 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。

    FINFET structures with fins recessed beneath the gate
    4.
    发明授权
    FINFET structures with fins recessed beneath the gate 有权
    FINFET结构，翅片凹陷在门下

    公开(公告)号：US09246003B2

    公开(公告)日：2016-01-26

    申请号：US14083517

    申请日：2013-11-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Eric C. Harley ,  Yue Ke ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L29/772 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    Abstract: A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

    Abstract translation: 半导体结构可以包括半导体鳍片，半导体鳍片上的栅极，栅极的侧壁上的间隔物，在间隔物下方的半导体鳍片的端部中的成角度的凹陷区域以及填充成角度的凹部的第一半导体区域。 成角度的凹槽可以是v形或西格玛形。 该结构还可以包括与第一半导体区域和衬底接触的第二半导体区域。 该结构可以通过在衬底上形成半导体翅片的一部分上方的栅极形成，在栅极的侧壁上形成间隔物; 除去未被间隔物或栅极覆盖的半导体鳍片的一部分以暴露翅片的侧壁，蚀刻翅片的侧壁以在间隔物下方形成倾斜的凹陷区域，并用第一外延半导体填充成角度的凹陷区域 地区。

    Graphene transistor with a sublithographic channel width
    5.
    发明授权
    Graphene transistor with a sublithographic channel width 有权
    具有亚光刻通道宽度的石墨烯晶体管

    公开(公告)号：US09236477B2

    公开(公告)日：2016-01-12

    申请号：US14181832

    申请日：2014-02-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jack O. Chu ,  Christos Dimitrakopoulos ,  Eric C. Harley ,  Judson R. Holt ,  Timothy J. McArdle ,  Matthew W. Stoker

    IPC: H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/785 ,  H01L21/0243 ,  H01L21/02447 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66795 ,  H01L29/7781

    Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion.

    Abstract translation: 硅碳合金结构可以通过选择性外延工艺形成为围绕半导体翅片的倒U形结构。 形成平坦化介电层以填充硅 - 碳合金结构之间的间隙。 在平坦化之后，硅 - 碳合金结构的剩余垂直部分构成可以具有亚光刻宽度的硅碳合金翅片。 半导体翅片可以用替换的介质材料翅片代替。 在一个实施例中，采用图案化掩模层，可以在每个硅 - 碳合金散热片的端部周围除去硅 - 碳合金散热片的侧壁。 执行退火以将硅碳合金翅片的表面部分隐藏成石墨烯层。 在一个实施例中，每个石墨烯层可以仅包括沟道区域中的水平部分，并且在源极和漏极区域中包括水平部分和侧壁部分。 如果不使用图案化掩模层，则每个石墨烯层可以仅包括水平部分。

    Method of inspecting a semiconductor substrate
    7.
    发明授权
    Method of inspecting a semiconductor substrate 有权
    检查半导体衬底的方法

    公开(公告)号：US09390884B2

    公开(公告)日：2016-07-12

    申请号：US14274042

    申请日：2014-05-09

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric C. Harley ,  Oliver D. Patterson ,  Kevin T. Wu

    IPC: H01L21/00 ,  H01J37/22 ,  H01J37/244 ,  G01N23/225 ,  G01B15/02

    CPC classification number: H01J37/222 ,  G01B15/02 ,  G01N23/2251 ,  H01J37/244 ,  H01J2237/063 ,  H01J2237/221 ,  H01J2237/24495 ,  H01J2237/24592

    Abstract: A semiconductor substrate inspection system includes an e-beam inspection system configured to deliver electrons to a specimen semiconductor substrate. A sensor is configured to detect reflected electrons that reflect off the surface of the specimen semiconductor substrate. An analysis unit is configured to determine a number of electrons received by the semiconductor substrate, and to determine at least one target region including at least one defect of the semiconductor substrate. A reference image module is in electrical communication with the analysis unit. The reference image module is configured to generate a first digital image having a plurality of pixels, and to adjust a gray-scale level of the pixels included in the target region based on the number electrons included in each pixel to generate a second digital image that excludes the at least one defect.

    Abstract translation: 半导体衬底检查系统包括被配置为将电子传递到样本半导体衬底的电子束检查系统。 传感器被配置为检测从样本半导体衬底的表面反射的反射电子。 分析单元被配置为确定由半导体衬底接收的电子数量，并且确定至少一个包括半导体衬底的至少一个缺陷的目标区域。 参考图像模块与分析单元电连通。 参考图像模块被配置为生成具有多个像素的第一数字图像，并且基于包括在每个像素中的数量的电子像素来调整包括在目标区域中的像素的灰度级别以产生第二数字图像， 排除至少一个缺陷。

    PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS
    8.
    发明申请
    PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS 审中-公开
    用于改善活性区域的电气隔离的部分氧化物

    公开(公告)号：US20160079397A1

    公开(公告)日：2016-03-17

    申请号：US14948977

    申请日：2015-11-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

    IPC: H01L29/66 ,  H01L21/762

    CPC classification number: H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

    Abstract: A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

    Abstract translation: 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。

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