Invention Grant
- Patent Title: Efficient cache management in a tiled architecture
- Patent Title (中): 在平铺架构中高效缓存管理
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Application No.: US14150394Application Date: 2014-01-08
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Publication No.: US09239795B2Publication Date: 2016-01-19
- Inventor: Mukesh Chand Agarwal , Narendra Keshav Rane
- Applicant: NVIDIA CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06T1/20 ; G06F9/38 ; G06F12/12 ; G06T1/60

Abstract:
A surface cache stores pixel data on behalf of a pixel processing pipeline that is configured to generate screen tiles. The surface cache assigns hint levels to cache lines storing pixel data according to whether that pixel data is likely to be needed again. When the pixel data is needed to process a subsequent tile, the corresponding cache line is assigned a higher hint value. When the pixel data is not needed again, the corresponding cache line is assigned a lower hint value. The surface cache is configured to preferentially evict cache lines having a lower hint value, thereby preserving cache lines that store pixel data needed for future processing. In addition, a fetch controller is configured to throttle the rate at which fetch requests are issued to the surface cache to prevent situations where pixel data needed for future operations becomes prematurely evicted.
Public/Granted literature
- US20150193903A1 EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE Public/Granted day:2015-07-09
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