Efficient cache management in a tiled architecture
    2.
    发明授权
    Efficient cache management in a tiled architecture 有权
    在平铺架构中高效缓存管理

    公开(公告)号:US09239795B2

    公开(公告)日:2016-01-19

    申请号:US14150394

    申请日:2014-01-08

    Abstract: A surface cache stores pixel data on behalf of a pixel processing pipeline that is configured to generate screen tiles. The surface cache assigns hint levels to cache lines storing pixel data according to whether that pixel data is likely to be needed again. When the pixel data is needed to process a subsequent tile, the corresponding cache line is assigned a higher hint value. When the pixel data is not needed again, the corresponding cache line is assigned a lower hint value. The surface cache is configured to preferentially evict cache lines having a lower hint value, thereby preserving cache lines that store pixel data needed for future processing. In addition, a fetch controller is configured to throttle the rate at which fetch requests are issued to the surface cache to prevent situations where pixel data needed for future operations becomes prematurely evicted.

    Abstract translation: 表面缓存代表被配置为生成屏幕贴图的像素处理流水线存储像素数据。 表面缓存根据该像素数据是否可能再次需要,将提示级别分配给存储像素数据的高速缓存行。 当需要像素数据来处理随后的图块时,相应的高速缓存行被分配更高的提示值。 当不再需要像素数据时,分配相应的高速缓存行较低的提示值。 表面缓存配置为优先驱逐具有较低提示值的高速缓存行,从而保留存储未来处理所需的像素数据的高速缓存行。 此外,提取控制器被配置为将发出提取请求的速率减小到表面缓存以防止未来操作所需的像素数据过早地被驱逐的情况。

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