发明授权
US09240786B2 Homogeneous dual-rail logic for DPA attack resistive secure circuit design
有权
均匀双轨逻辑DPA攻击电阻安全电路设计
- 专利标题： Homogeneous dual-rail logic for DPA attack resistive secure circuit design
- 专利标题（中）： 均匀双轨逻辑DPA攻击电阻安全电路设计
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申请号： US13794775申请日： 2013-03-11
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公开(公告)号： US09240786B2公开(公告)日： 2016-01-19
- 发明人: Kazuyuki Tanimura , Nikil Dutt
- 申请人： Kazuyuki Tanimura , Nikil Dutt
- 申请人地址： US CA Oakland
- 专利权人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- 当前专利权人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- 当前专利权人地址： US CA Oakland
- 代理机构： One LLP
- 主分类号： H03K19/00
- IPC分类号： H03K19/00 ; H03K19/003 ; H03K19/096
摘要：
Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HURL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HURL circuit has a differential power at a level that is resistive to DPA attacks.
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