Invention Grant
US09244747B2 System and method for providing dynamic clock and voltage scaling (DCVS) aware interprocessor communication
有权
提供动态时钟和电压缩放(DCVS)的处理器间通信的系统和方法
- Patent Title: System and method for providing dynamic clock and voltage scaling (DCVS) aware interprocessor communication
- Patent Title (中): 提供动态时钟和电压缩放(DCVS)的处理器间通信的系统和方法
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Application No.: US14210064Application Date: 2014-03-13
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Publication No.: US09244747B2Publication Date: 2016-01-26
- Inventor: Krishna Vsssr Vanka , Shirish Kumar Agarwal , Sravan Kumar Ambapuram
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Smith Risley Tempel Santos LLC
- Main IPC: G06F9/54
- IPC: G06F9/54 ; G06F1/32

Abstract:
Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.
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