Invention Grant
- Patent Title: Test pattern optimization for LDPC based flawscan
- Patent Title (中): 基于LDPC的瑕疵的测试模式优化
-
Application No.: US13672218Application Date: 2012-11-08
-
Publication No.: US09246519B2Publication Date: 2016-01-26
- Inventor: Jefferson E. Singleton , Shaohua Yang , Bruce A. Wilson , Keenan T. O'Brien
- Applicant: LSI Corporation
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: G06F11/263
- IPC: G06F11/263 ; H03M13/00 ; H03M13/11 ; H03M13/35

Abstract:
A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium.
Public/Granted literature
- US20140129890A1 Test Pattern Optimization for LDPC Based Flawscan Public/Granted day:2014-05-08
Information query