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1472 条记录 (耗时 0.024 秒)

    Embedded pattern generator
    2.
    发明授权
    Embedded pattern generator 有权

    公开(公告)号：US12119826B2

    公开(公告)日：2024-10-15

    申请号：US17849417

    申请日：2022-06-24

    申请人： Texas Instruments Incorporated

    发明人： Srinivasa Chakravarthy ,  Prasanth Viswanathan Pillai ,  Mohammed Arif ,  Bhargov Bora

    IPC分类号： H03K5/00 ,  G06F1/06 ,  G06F11/263 ,  H03K21/02

    CPC分类号： H03K5/00006 ,  G06F1/06 ,  G06F11/263 ,  H03K21/02

    摘要： An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

    AUTOMATIC LEARNING METHOD AND SYSTEM FOR DIGITAL TEST VECTOR
    5.
    发明公开
    AUTOMATIC LEARNING METHOD AND SYSTEM FOR DIGITAL TEST VECTOR 审中-公开

    公开(公告)号：US20240248820A1

    公开(公告)日：2024-07-25

    申请号：US17801525

    申请日：2022-04-18

    申请人： Macrotest Semiconductor Inc.

    发明人： Wanchao Liu ,  Guoliang Mao

    IPC分类号： G06F11/22 ,  G06F11/263

    CPC分类号： G06F11/2221 ,  G06F11/263

    摘要： The present disclosure discloses an automatic learning method and system for a digital test vector. The system includes an upper computer, a pattern generator PG, a driver DRIVER, a comparator COMPARE and a history random access memory HRAM. The method includes: writing a pattern file, the pattern file including an input pin timing and an output pin timing, wherein the input pin timing is provided by a device under test, and the output pin timing is configured to be in a learning state; running the pattern file, and recording a running state; reading recorded running state data, and acquiring an output pin state, recorded within certain time, in the running state data; and correcting the output pin timing in the running pattern file according to the acquired output pin state to obtain a corrected output timing, thus obtaining a corrected pattern file. The present disclosure greatly improves the development efficiency, reduces writing of the characteristic of an output pin of a chip, and lowers the writing difficulty.

    Method for detecting a fault injection in a data processing system
    6.
    发明授权
    Method for detecting a fault injection in a data processing system 有权

    公开(公告)号：US12032684B2

    公开(公告)日：2024-07-09

    申请号：US17648041

    申请日：2022-01-14

    申请人： NXP B.V.

    发明人： Lars Kaufmann ,  Nikita Veshchikov

    IPC分类号： G06F21/54 ,  G06F11/263

    CPC分类号： G06F21/54 ,  G06F11/263 ,  G06F2221/033

    摘要： A method for detecting a fault injection is described. The method includes providing a secondary code, the secondary code including a predetermined function with a known expected result when the secondary code is executed with a known tested input. A primary code is executed in the data processing system. The primary code may be a portion of code that requires protection from a fault injection attack, such as for example, security sensitive code. The secondary code is executed in parallel with the primary code execution in the data processing system to produce an output. The output is compared with the known expected result to detect the fault injection attack of the data processing system. In one embodiment, the secondary code is not related to the primary code.

    METHOD AND SYSTEM FOR FIRMWARE FUNCTIONALITY TESTING OF GAS DETECTOR DEVICES
    7.
    发明公开
    METHOD AND SYSTEM FOR FIRMWARE FUNCTIONALITY TESTING OF GAS DETECTOR DEVICES 审中-公开

    公开(公告)号：US20240143467A1

    公开(公告)日：2024-05-02

    申请号：US18483165

    申请日：2023-10-09

    申请人： HONEYWELL INTERNATIONAL INC.

    发明人： Sumit Suresh KULKARNI ,  Renjith GEORGE ,  Jayakumar SUBBAIYAN

    IPC分类号： G06F11/263 ,  G06F11/273 ,  G06F11/30

    CPC分类号： G06F11/2635 ,  G06F11/2733 ,  G06F11/3072

    摘要： Various embodiments are directed to methods, apparatuses, and systems for performing firmware functionality testing of a gas detector device, comprising: for each gas of one or more gases; applying selected test data from test data stored locally on the gas detector device, wherein the selected test data comprise simulated sensor data and is selected based at least in part on the gas; generating one or more output signals based at least in part on processing the selected test data; and generating testing output data based at least in part on comparing the one or more output signals to one or more expected output signals for the selected test data, wherein the testing output data comprise data indicative of performance of one or more firmware functionalities of the gas detector device with respect to the gas.

    Saturation of multiple PCIe slots in a server by multiple ports in a single test card
    8.
    发明授权
    Saturation of multiple PCIe slots in a server by multiple ports in a single test card 有权

    公开(公告)号：US11966309B2

    公开(公告)日：2024-04-23

    申请号：US17854609

    申请日：2022-06-30

    申请人： Hewlett Packard Enterprise Development LP

    发明人： Hong-Jen Hsu ,  Chih-Kang Lin

    IPC分类号： G06F11/00 ,  G06F11/22 ,  G06F11/263 ,  G06F11/273

    CPC分类号： G06F11/263 ,  G06F11/2221 ,  G06F11/2733

    摘要： One aspect provides a method and system for saturation of multiple I/O slots by multiple testing ports and verification of link health in between. During operation, the system detects a testing card with a plurality of test ports which are coupled to a plurality of input/output (I/O) slots of a computing device. The system communicates with the plurality of test ports via the plurality of I/O slots. The system generates, by the computing device, a script for each test port, wherein the script comprises a series of read and write operations to be executed by the testing card on a memory device associated with the computing device. The system allows the plurality of test ports to execute the script and perform the corresponding read operations and write operations, thereby facilitating testing of the I/O slots of the computing device in parallel by the test ports of the single testing card.

    SYSTEMS AND METHODS FOR CLOUD-BASED TESTING OF POS DEVICES
    10.
    发明公开
    SYSTEMS AND METHODS FOR CLOUD-BASED TESTING OF POS DEVICES 审中-公开

    公开(公告)号：US20240086289A1

    公开(公告)日：2024-03-14

    申请号：US18515937

    申请日：2023-11-21

    申请人： Worldpay, LLC

    发明人： Walter BANKS

    IPC分类号： G06F11/26 ,  G06F11/263 ,  G06Q20/20

    CPC分类号： G06F11/261 ,  G06F11/263 ,  G06Q20/20

    摘要： A computer-implemented method for cloud-based testing of a payment network may include receiving a test configuration for testing a payment processing network, configuring a simulated worker generator for generating a plurality of simulated workers according to the received test configuration, reading commands to be executed by each simulated worker among the plurality of simulated workers from a command bank according to the received test configuration, configuring the plurality of simulated workers according to the commands and the received test configuration, starting a swarm test of the payment processing network by the plurality of simulated workers, reading results of the swarm test from the plurality of simulated workers, and saving the results to storage.