公开(公告)号：US11599435B2

公开(公告)日：2023-03-07

申请号：US16540080

申请日：2019-08-14

申请人： VMware, Inc.

发明人： Yu Wu ,  Yang Yang ,  Xiang Yu ,  Wenguang Wang ,  Jin Feng

IPC分类号： G06F11/07 ,  G06F11/30 ,  G06F11/22 ,  G06F11/263 ,  G06N5/00 ,  G06F16/22 ,  G06N5/04 ,  G06F9/455

摘要： A failure analysis system identifies a root cause of a failure (or other health issue) in a virtualized computing environment and provides a recommendation for remediation. The failure analysis system uses a model-based reasoning (MBR) approach that involves building a model describing the relationships/dependencies of elements in the various layers of the virtualized computing environment, and the model is used by an inference engine to generate facts and rules for reasoning to identify an element in the virtualized computing environment that is causing the failure. Then, then the failure analysis system uses a decision tree analysis (DTA) approach to perform a deep diagnosis of the element, by traversing a decision tree that was generated by combining the rules for reasoning provided by the MBR approach, in conjunction with examining data collected by health monitors. The result of the DTA approach is then used to generate the recommendation for remediation.

公开(公告)号：US11573270B2

公开(公告)日：2023-02-07

申请号：US17365822

申请日：2021-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guenole Jan ,  Huanlong Liu ,  Jian Zhu ,  Yuan-Jen Lee ,  Po-Kang Wang

IPC分类号： G01R31/319 ,  G11C29/14 ,  G11C29/38 ,  G11C29/12 ,  G01R31/3167 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/263 ,  G11C11/16 ,  H03M1/12

摘要： A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

公开(公告)号：US11567855B1

公开(公告)日：2023-01-31

申请号：US17015778

申请日：2020-09-09

申请人： Two Six Labs, LLC

发明人： Austin Fletcher ,  Daniel Su ,  Bradley Boccuzzi

IPC分类号： G06F11/36 ,  G06F11/263 ,  G06F11/277

摘要： An automated fault injection testing and analysis approach drives fault injection into a processor driven instruction sequence to quantify and define susceptibility to external fault injections for manipulating instruction execution and control flow of a set of computer instructions. A fault injection such as a voltage or electromagnetic pulse directed at predetermined locations on a processor (Central Processing Unit, or CPU) alters a result of a processor instruction to change values or execution paths. One or more quantified injections define an injection chain that causes a predictable or repeatable deviant result from an expected execution path through the code executed by the processor. Based on accumulation of fault injections and results, a repeatable injection chain and probability identifies an external action taken on a processing device to cause unexpected results that differ from an expected execution of a program or set of computer instructions.

公开(公告)号：US11520653B2

公开(公告)日：2022-12-06

申请号：US17071941

申请日：2020-10-15

申请人： NXP USA, Inc.

发明人： Neha Srivastava ,  Ankur Behl ,  Garima Sharda

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/263

摘要： A system-on-chip (SoC) is disclosed. The SoC includes a fault controlling circuit and processing circuits. The fault controlling circuit is configured to receive fault events generated by fault sources of the SoC and categorize the fault events based on a priority associated with each fault event. The fault controlling circuit is further configured to identify corresponding fault reactions for the categorized fault events and generate a set of recovery signals based on the identified fault reactions. The processing circuits are configured to receive the fault events, and further configured to receive the set of recovery signals to recover from the fault events. The fault controlling circuit thus acts as a central control system for controlling faults in the SoC.

公开(公告)号：US20220365857A1

公开(公告)日：2022-11-17

申请号：US17320025

申请日：2021-05-13

申请人： NVIDIA Corporation

发明人： Sailendra Chadalavada ,  Anitha Kalva ,  Abilash Nerallapally ,  Milind Sonawane ,  Shantanu Sarangi ,  Ashok Aravamudhan ,  Sridharan Ramakrishnan ,  Sam Edirisooriya ,  Hari Krishnan

IPC分类号： G06F11/263 ,  G06F11/27 ,  G06F11/273 ,  G06F11/14

摘要： During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.

公开(公告)号：US20220334937A1

公开(公告)日：2022-10-20

申请号：US17581022

申请日：2022-01-21

申请人： QA CONSULTANTS INC.

发明人： Toni JARDINI ,  Spencer REUBEN ,  Farsam FARZADPOUR ,  Akramul AZIM ,  Amalnnath PARAMESWARAN ,  Ansh DAVID ,  Bradley WOOD

IPC分类号： G06F11/263 ,  G06F11/22 ,  G06F11/273 ,  G06F11/34

摘要： There is provided a system and method for performing system integration on an embedded system of a connected and/or autonomous vehicle. Integration testing may include obtaining one or more requirements and/or specifications for a system under test; generating a metamodel based on the requirements and/or specifications; generating test cases based on the metamodel; prioritizing said test cases based on hazards associated with said test cases; executing one or more of said prioritized test cases; and obtaining a verdict for each of said one or more prioritized test cases.

公开(公告)号：US20220283919A1

公开(公告)日：2022-09-08

申请号：US17683672

申请日：2022-03-01

申请人： Innovative Defense Technologies, LLC

发明人： Bernard GAUF ,  Apostolos TOPALIS ,  Jacob HARRIS

IPC分类号： G06F11/263 ,  G06F11/34

摘要： An embodiment of the present invention is directed to a novel approach of applying Machine Learning, statistical methods and/or other algorithms to identify associations of input conditions and values with results of requirements, measures of performance assessments, and/or other indications. These associations may be provided to an analyst, system designer, other recipient and/or receiving system or component to inform of input conditions and values that uncover system sensitivities.

公开(公告)号：US11436115B2

公开(公告)日：2022-09-06

申请号：US16541567

申请日：2019-08-15

申请人： Delta Electronics (Thailand) Public Company Limited

发明人： Chin Huat Lim ,  Ming-Li Shiu ,  Adisak Paepoot ,  Narut Udomchoke

IPC分类号： G06F11/00 ,  G06F11/263 ,  G06F11/22 ,  G06F11/36 ,  G06F11/30

摘要： The present disclosure discloses a design and test method of a test plan. The test plan includes the plurality of input parameters, the plurality of output parameters, the plurality of system parameters, all of the numerical levels or the types of each input parameter, each output parameter and each system parameter. The test plan includes a plurality of test cases to cover combination conditions including a great number of the input parameters, the output parameters and the system parameters and their dynamic cross of the parameters. The design and test method performs the test cases of the test plan on the product automatically by considering overall possibly parameters and their levels associated with the product. The overall possibly parameters and their levels associated with the product can be tested before the product is dispatched to the customer so as to enhance the product quality.

公开(公告)号：US20220206912A1

公开(公告)日：2022-06-30

申请号：US17139350

申请日：2020-12-31

申请人： HEADSPIN, INC.

发明人： SEVERIN SMITH ,  THOMAS HOBSON ,  ELIAS PSCHERNIG ,  BRIEN COLWELL

IPC分类号： G06F11/22 ,  G06F11/263

摘要： An enclosure for testing performance of an application contains one or more devices. A first device being tested presents output using a display or a speaker. A camera or microphone, which may be associated with a second device in the enclosure, acquires information regarding the output, such as by acquiring data representing the display output of the first device using a camera. An interface presenting information regarding the performance of the application includes information determined using the camera or microphone, which may be useful when the first device is unable to directly capture the output that is presented. In other cases, a second device in the enclosure may provide a display output or an audio output, and the first device may receive the output using a camera or microphone, enabling the performance of the application relating to receipt of input by the first device to be tested.

公开(公告)号：US11372739B2

公开(公告)日：2022-06-28

申请号：US17001184

申请日：2020-08-24

申请人： International Business Machines Corporation

发明人： Paul E. Schardt ,  Jim C. Chen ,  Lance G. Thompson ,  James E. Carey

IPC分类号： G06F11/263 ,  G06F13/40 ,  G06F11/22

摘要： An accelerator manager monitors and logs performance of multiple accelerators, analyzes the logged performance, determines from the logged performance of a selected accelerator a desired programmable device for the selected accelerator, and specifies the desired programmable device to one or more accelerator developers. The accelerator manager can further analyze the logged performance of the accelerators, and generate from the analyzed logged performance an ordered list of test cases, ordered from fastest to slowest. A test case is selected, and when the estimated simulation time for the selected test case is less than the estimated synthesis time for the test case, the test case is simulated and run. When the estimated simulation time for the selected test case is greater than the estimated synthesis time for the text case, the selected test case is synthesized and run.