Invention Grant
US09252244B2 Methods of selectively growing source/drain regions of fin field effect transistor and method of manufacturing semiconductor device including a fin field effect transistor
有权
选择性地增长鳍状场效应晶体管的源极/漏极区域的方法及制造包括鳍状场效应晶体管的半导体器件的方法
- Patent Title: Methods of selectively growing source/drain regions of fin field effect transistor and method of manufacturing semiconductor device including a fin field effect transistor
- Patent Title (中): 选择性地增长鳍状场效应晶体管的源极/漏极区域的方法及制造包括鳍状场效应晶体管的半导体器件的方法
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Application No.: US14498996Application Date: 2014-09-26
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Publication No.: US09252244B2Publication Date: 2016-02-02
- Inventor: JinBum Kim , Seong Hoon Jeong , Jeon Il Lee , Seokhoon Kim , Kwan Heum Lee , Choeun Lee , Yu-Jin Pyo
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: KR10-2014-0007351 20140121
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; H01L29/51 ; H01L29/161 ; H01L21/02 ; H01L29/78 ; H01L21/8238 ; H01L21/8234 ; H01L27/12
Abstract:
The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.
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