Invention Grant
- Patent Title: Method and structure of packaging semiconductor devices
- Patent Title (中): 封装半导体器件的方法和结构
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Application No.: US14321500Application Date: 2014-07-01
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Publication No.: US09257341B2Publication Date: 2016-02-09
- Inventor: Mark A. Gerber
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; Frank D. Cimino
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/56 ; H01L23/00 ; H01L23/16 ; H01L23/31

Abstract:
A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.
Public/Granted literature
- US20150008583A1 Method and Structure of Packaging Semiconductor Devices Public/Granted day:2015-01-08
Information query
IPC分类: