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    Method and Structure of Packaging Semiconductor Devices
    1.
    发明申请
    Method and Structure of Packaging Semiconductor Devices 有权
    封装半导体器件的方法和结构

    公开(公告)号：US20150008583A1

    公开(公告)日：2015-01-08

    申请号：US14321500

    申请日：2014-07-01

    Applicant: Texas Instruments Incorporated

    Inventor： Mark A. Gerber

    IPC: H01L21/78 ,  H01L21/768 ,  H01L21/56 ,  H01L23/28 ,  H01L23/482

    CPC classification number: H01L23/34 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49534 ,  H01L23/53209 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.

    Abstract translation: 一种制造封装半导体器件的方法; 将具有开口的批量尺寸的金属网格附接到具有被一层可UV剥离的粘合剂覆盖的绝缘透明芯的胶带上，所述开口的尺寸大于半导体芯片; 将半导体芯片附接到每个窗口的带上，所述芯片端子面向粘合剂表面; 具有低热膨胀系数的层压绝缘材料，以填充每个芯片与相应网格之间的间隙; 翻转组件以将载体放置在芯片的背面和层压之下并且去除带子; 等离子体清洗组件正面并溅射均匀化整个组件上的至少一个金属层; 可选地镀金属层; 并且图案化金属层以形成重新布线迹线和用于组装的扩展接触垫。

    PACKAGED SEMICONDUCTOR DEVICES
    6.
    发明申请
    PACKAGED SEMICONDUCTOR DEVICES 审中-公开
    包装半导体器件

    公开(公告)号：US20160111349A1

    公开(公告)日：2016-04-21

    申请号：US14978586

    申请日：2015-12-22

    Applicant: Texas Instruments Incorporated

    Inventor： Mark A. Gerber

    IPC: H01L23/34 ,  H01L23/495 ,  H01L23/482 ,  H01L23/532

    CPC classification number: H01L23/34 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49534 ,  H01L23/53209 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material adheres to at the sidewalls of the chip. The frame has a first surface planar with the first chip surface and a parallel second surface planar with the second chip surface. The first frame surface includes one or more embedded metallic fiducials extending from the first surface to the insulating material. At least one film of sputtered metal extends from the terminals across the surface of the polymeric layer to the fiducials. The film is patterned to form extended contact pads over the frame and rerouting traces between the chip terminals and the extended contact pads. The film adheres to the surfaces.

    Abstract translation: 半导体器件具有半导体芯片，其具有带金属化端子的第一表面和平行的第二表面。 绝缘材料框架粘附在芯片的侧壁处。 框架具有与第一芯片表面平面的第一表面和与第二芯片表面平行的平行的第二表面。 第一框架表面包括从第一表面延伸到绝缘材料的一个或多个嵌入金属基准。 至少一个溅射金属膜从端子穿过聚合物层的表面延伸到基准。 图案化膜以在框架上形成扩展的接触焊盘，并且在芯片端子和扩展的接触焊盘之间重新布线。 膜粘附在表面上。

    Method and structure of packaging semiconductor devices
    9.
    发明授权
    Method and structure of packaging semiconductor devices 有权
    封装半导体器件的方法和结构

    公开(公告)号：US09257341B2

    公开(公告)日：2016-02-09

    申请号：US14321500

    申请日：2014-07-01

    Applicant: Texas Instruments Incorporated

    Inventor： Mark A. Gerber

    IPC: H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

    CPC classification number: H01L23/34 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49534 ,  H01L23/53209 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.

    Abstract translation: 一种制造封装半导体器件的方法; 将具有开口的批量尺寸的金属网格附接到具有被一层可UV剥离的粘合剂覆盖的绝缘透明芯的胶带上，所述开口的尺寸大于半导体芯片; 将半导体芯片附接到每个窗口的带上，所述芯片端子面向粘合剂表面; 具有低热膨胀系数的层压绝缘材料，以填充每个芯片与相应网格之间的间隙; 翻转组件以将载体放置在芯片的背面和层压之下并且去除带子; 等离子体清洗组件正面并溅射均匀化整个组件上的至少一个金属层; 可选地镀金属层; 并且图案化金属层以形成重新布线迹线和用于组装的扩展接触垫。

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