Invention Grant
- Patent Title: Semiconductor construction forming methods
- Patent Title (中): 半导体施工成型方法
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Application No.: US14680431Application Date: 2015-04-07
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Publication No.: US09257430B2Publication Date: 2016-02-09
- Inventor: Jun Liu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/102 ; G11C13/00 ; H01L27/24 ; H01L29/872 ; H01L29/66
Abstract:
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.
Public/Granted literature
- US20150214481A1 Memory Device Constructions, Memory Cell Forming Methods, and Semiconductor Construction Forming Methods Public/Granted day:2015-07-30
Information query
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