An oscillator of a phase-locked loop (PLL) or frequency-locked loop (FLL) may include two inputs. The two inputs may include a first analog input and a second digital input. The second digital input may receive a digital signal setting a desired output clock frequency of the oscillator and/or indicating an approximate frequency of frequency range for output by the oscillator. The first analog input may receive a voltage representative of a desired frequency for the output clock frequency of the PLL or FLL to fine-tune the output frequency from the approximate frequency set by the second digital input. The first analog input may be generated from a master clock input signal. When the master clock input signal disappears, the second digital signal controls the output frequency of the oscillator to allow redundant operation of the PLL or FLL even when no master clock input signal is present.