A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.