公开(公告)号：US09263143B2

公开(公告)日：2016-02-16

申请号：US14330106

申请日：2014-07-14

Applicant: Macronix International Co., Ltd.

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Chen-Jun Wu

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  H01L27/115

CPC classification number: G11C16/16 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.

Abstract translation: 一种三维（3D）存储器件的数据擦除方法，包括以下步骤。 首先，在擦除操作的第一阶段中，将第一电压施加到半导体通道的第一半导体通道，以擦除存储在第一半导体通道上限定的存储单元中的数据，并将第二电压施加到第二半导体通道 的半导体通道，其中第二半导体沟道与第一半导体沟道相邻。 然后，在擦除操作的第二阶段中，将第二电压施加到第一半导体沟道，并将第一电压施加到第二半导体沟道。

公开(公告)号：US10381094B2

公开(公告)日：2019-08-13

申请号：US15290376

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chen-Jun Wu ,  Chih-Chang Hsieh ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10

Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i−1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i−1).

公开(公告)号：US20160012901A1

公开(公告)日：2016-01-14

申请号：US14330106

申请日：2014-07-14

Applicant: Macronix International Co., Ltd.

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Chen-Jun Wu

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.

Abstract translation: 一种三维（3D）存储器件的数据擦除方法，包括以下步骤。 首先，在擦除操作的第一阶段中，将第一电压施加到半导体通道的第一半导体通道，以擦除存储在第一半导体通道上限定的存储单元中的数据，并将第二电压施加到第二半导体通道 的半导体通道，其中第二半导体沟道与第一半导体沟道相邻。 然后，在擦除操作的第二阶段中，将第二电压施加到第一半导体沟道，并将第一电压施加到第二半导体沟道。