A semiconductor device comprising a second surface of a logic die and a second surface of a via bar coupled to a first surface of a substrate, a second surface of a memory die coupled to a first surface of the via bar, a portion of the second surface of the memory die extending over the first surface of the logic die, such that the logic die and the memory die are vertically staggered, and the memory die electrically coupled to the logic die through the via bar. The via bar can be formed from glass, and include through-glass vias (TGVs) and embedded passives such as resistors, capacitors, and inductors. The semiconductor device can be formed as a single package or a package-on-package structure with the via bar and the memory die encapsulated in a package and the substrate and logic die in another package.