Invention Grant
- Patent Title: Semiconductor package with multi-level die block
- Patent Title (中): 半导体封装具有多级模块
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Application No.: US14013112Application Date: 2013-08-29
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Publication No.: US09275944B2Publication Date: 2016-03-01
- Inventor: Kok Chai Goh
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L23/13
- IPC: H01L23/13 ; H01L23/495 ; H01L23/00 ; H01L25/065

Abstract:
A semiconductor package includes a block having a first side, a second side opposite the first side and a recessed region extending from the second side toward the first side so that the block has a thinner part in the recessed region and a thicker part outside the recessed region. The semiconductor package further includes a first semiconductor die and a second semiconductor die each having opposing first and second sides. The first semiconductor die is disposed in the recessed region of the block and attached to the thinner part of the block at the first side of the first semiconductor die. The second semiconductor die is attached to the second side of the first semiconductor die at a first side of the second semiconductor die.
Public/Granted literature
- US20150061096A1 Semiconductor Package with Multi-Level Die Block Public/Granted day:2015-03-05
Information query
IPC分类: