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    Electronic device with multi-layer contact and system
    3.
    发明授权
    Electronic device with multi-layer contact and system 有权

    公开(公告)号：US12255168B2

    公开(公告)日：2025-03-18

    申请号：US18509357

    申请日：2023-11-15

    Applicant: Infineon Technologies AG

    Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

    IPC: H01L29/43 ,  H01L23/00 ,  H01L23/482 ,  H01L23/495 ,  H01L29/45

    Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

    High power single-die semiconductor package
    5.
    发明授权
    High power single-die semiconductor package 有权
    大功率单芯片半导体封装

    公开(公告)号：US09054063B2

    公开(公告)日：2015-06-09

    申请号：US13857252

    申请日：2013-04-05

    Applicant: Infineon Technologies AG

    Inventor： Kok Chai Goh ,  Meng Tong Ong

    IPC: H01L23/34 ,  H01L21/78 ,  H01L23/31 ,  H01L23/36 ,  H01L23/492 ,  H01L21/683

    CPC classification number: H01L23/34 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/36 ,  H01L23/492 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/73253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die.

    Abstract translation: 半导体封装包括单个半导体管芯和导电和导热基座。 单个半导体管芯包括具有相对的第一和第二表面以及第一和第二表面之间的绝缘侧的半导体本体。 单个半导体管芯还包括在第一表面处的第一电极和在第二表面处的第二电极。 单个半导体管芯具有在第一和第二表面之间测量的限定厚度，沿着绝缘侧中的一个测量的限定宽度，以及沿另一个绝缘侧测量的限定长度。 基座在单个半导体管芯的第二表面处附接到第二电极，并且具有与单个半导体管芯相同的长度和宽度。

    High Power Single-Die Semiconductor Package
    9.
    发明申请
    High Power Single-Die Semiconductor Package 有权
    大功率单模半导体封装

    公开(公告)号：US20140299981A1

    公开(公告)日：2014-10-09

    申请号：US13857252

    申请日：2013-04-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Kok Chai Goh ,  Meng Tong Ong

    IPC: H01L23/34 ,  H01L21/78

    CPC classification number: H01L23/34 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/36 ,  H01L23/492 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/73253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die.

    Abstract translation: 半导体封装包括单个半导体管芯和导电和导热基座。 单个半导体管芯包括具有相对的第一和第二表面以及第一和第二表面之间的绝缘侧的半导体本体。 单个半导体管芯还包括在第一表面处的第一电极和在第二表面处的第二电极。 单个半导体管芯具有在第一和第二表面之间测量的限定厚度，沿着绝缘侧中的一个测量的限定宽度，以及沿另一个绝缘侧测量的限定长度。 基座在单个半导体管芯的第二表面处附接到第二电极，并且具有与单个半导体管芯相同的长度和宽度。

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