Invention Grant
- Patent Title: Nanowire and planar transistors co-integrated on utbox SOI substrate
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Application No.: US14266999Application Date: 2014-05-01
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Publication No.: US09276073B2Publication Date: 2016-03-01
- Inventor: Sylvain Barraud , Yves Morand
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS (CROLLES 2) SAS
- Applicant Address: FR Paris FR Crolles
- Assignee: Commissariat a l'énergie atomique et aux énergies alternatives,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: Commissariat a l'énergie atomique et aux énergies alternatives,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: FR Paris FR Crolles
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1354045 20130502
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L29/06 ; H01L29/41 ; H01L51/05 ; H01L51/44 ; H01L29/786 ; H01L27/12

Abstract:
Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
Public/Granted literature
- US20140326955A1 PLANAR TRANSISTORS WITH NANOWIRES COINTEGRATED ON A SOI UTBOX SUBSTRATE Public/Granted day:2014-11-06
Information query
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