A memory device includes latching circuitry for receiving a latching value and for providing said latching value as an output. A path receives said latching value and passes said latching value to said latching circuitry. First storage circuitry provides a first stored value when said memory device is in a read mode of operation. A bit line is connected to said first storage circuitry. First control circuitry selectively connects said bit line to said path. Sensing circuitry, when an enable signal is active, detects a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and outputs a latching value, dependent on said voltage change, on said path. Second storage circuitry provides a second stored value in a test mode of operation and second control circuitry receives said second stored value and selectively outputs said second stored value as said latching value on said path. Said latching circuitry outputs said latching value as said output in dependence on said enable signal, such that said enable signal controls both said latching circuitry and said sense circuitry.